This invention relates to an offset calibration system for an integrated analog to digital converter (ADC) and digital to analog converter (DAC) with full-scale ranges not related by a power of two.
Analog to digital converters (ADCs) often have significant offset errors. That is, for a zero input there will not be a zero output. The difference is the offset. To compensate for the offset an ADC may be calibrated by introducing a zero input to the ADC to determine the offset, then subtracting the offset from the ADC output during normal operation to remove the error.
Digital to analog converters (DACs) also often have significant offset errors. When used together in a circuit with a calibrated ADC, a DAC may be calibrated to compensate for its offset. The DAC input is set to zero; its analog output represents the offset error and is fed to the input of the ADC. The output of the calibrated ADC is thus representative of the offset error of the DAC. During normal operation, the DAC offset, measured using the ADC, is subtracted from input codes. This approach has worked well. However, when the ADC and DAC least significant bits (LSBs) do not correspond to the same voltage, the offset error of the DAC measured using the ADC must be adjusted by the ratio of the LSB voltages to obtain the proper offset correction for the DAC. When the ADC and DAC full-scale ranges are equal or related by a power of two, the adjustment may be performed by shifting the ADC output (represented as a binary number) left or right. Shifting the ADC output left effectively multiplies the value by a power of two. Shifting the output right divides the value by a power of two. When the full-scale ranges are not related by a power of two, the adjustment may be accomplished by multiplication and division. However, multiplication and division by numbers that are not powers of two requires fairly large digital circuits.
It is therefore an object of this invention to provide an improved offset calibration system.
It is a further object of this invention to provide such an improved offset calibration system for an analog to digital converter and digital to analog converter having full-scale ranges not related by a power of two.
It is a further object of this invention to provide such an improved offset calibration system which accommodates the differing ranges without employing a division by a number that is not a power of two.
It is a further object of this invention to provide such an improved offset calibration system which accommodates the differing ranges without employing a multiplication by a number that is not a power of two.
It is a further object of this invention to provide such an improved offset calibration system which can accomplish its calibration function primarily using circuits that are needed for normal operation such as accumulators used to implement the decimators for a delta-sigma ADC.
The invention results from the realization that a simple, effective offset calibration system for an integrated analog to digital converter and digital to analog converter with different ranges which avoids multiplication and division by numbers that are not powers of two can be achieved by accumulating a predetermined number of offset compensated analog to digital output values and dividing them by a preselected power of two in the ratio of the ADC LSB voltage to the DAC LSB voltage.
This invention features an offset calibration system including an analog to digital converter having a first full-scale range with a first offset compensation circuit and a digital to analog converter having a second full-scale range with a second offset compensation circuit. The digital to analog converter has its output connected to the input of the analog to digital converter during calibration of the digital to analog converter. A range adjustment circuit accumulates a predetermined number of analog to digital output values and divides the accumulated values by a preselected power of 2 in the ratio of the voltage corresponding to the analog to digital converter least significant bit to the voltage corresponding to the digital to analog converter least significant bit.
In a preferred embodiment the range adjustment circuit may include an accumulator circuit for accumulating the predetermined number of analog to digital output values. The accumulator circuit may include a control circuit for determining the number of analog to digital output values to be accumulated. The accumulator circuit may include a register and means for selecting the stages of the register representing the quotient of the division of the accumulated values by the preselected power of 2. The analog to digital converter may be calibrated before the digital to analog converter is calibrated. The accumulator circuit may operate as digital filter during normal operation.